ATE Vision 2020 2007 - Preliminary Call for Papers

CALL FOR PAPERS

Scope -- Author Information -- Committees

Scope

The workshop will examine where the ATE industry is heading in the near-term as well as in the long-term. Integrated circuits get denser, larger, and faster and more heterogeneous. As the number of dies in a single package increases, so does the test quality target. Certain dies require Known-Good-Die (KGD) quality levels, whereas more complex failure modes already challenge our yield learning curves.

These issues, when added to increasing Cost-Of-Test (COT), Time-To-Volume (TTV), and Time-To-Market (TTM) pressures, driven by today’s high-volume market applications, pose significant challenges to the ATE industry. To meet those challenges the industry needs to innovate in areas such as test methodologies, interconnection technologies, architectures, and Design-For-Testability (DFT) and Design-For-Manufacturability (DFM) technologies.

The goal of this workshop is to create an informal forum to discuss those innovations relevant to ATE developers and users. We are looking for solutions to the issues of 2010 and beyond, not those of 2008. Are our roadmaps addressing future test challenges? Are we investing our research dollars in the right areas? Do we have the right business models in place to succeed in the future? Join the discussion!

Representative topics include, but are not limited to:

Design for Testability (BIST, BISR)
Test methods for future defects
Adaptive Design Techniques
ATE/EDA Link
High-speed IO ATE
Low-cost ATE
RF ATE
ATE for Statistical Test

Author Information

top

To present at the Workshop, authors are invited to submit presentation proposals. The proposals may be draft presentations, extended abstracts (500 words), or full papers. Each submission should include: title, full name and affiliation of all authors, a short abstract of 50 words, and keywords. Also, identify a contact author and include a complete correspondence address, phone number, fax number, and e-mail address.

Submit a copy of your presentation proposal by Postscript, or PDF, via E-mail. Proposals for panel discussions are also invited. Submissions are due no later than August 21st, 2007.

Submit your paper proposal to:

Scott Davidson, Sun Microsystems E-mail: scott.davidson@sun.com Tel: +1-408-992-3113

Authors will be notified of the disposition of their papers by September 18th, 2007.

Authors of accepted papers may submit the final presentation by October 3rd, 2007 for inclusion in the Workshop Notes, which will be provided to the attendees. Optionally, an extended abstract or paper can also be included in the notes.

For general information contact:

Erik Volkerink
Verigy
Tel: +1-408-864-7661

Committees

top

General Chair
E. Volkerink, Verigy

General Co-Chair
Yervant Zorian, Virage Logic

Program Chair
S. Davidson, Sun Microsystems

Program Co-Chair
M. Kondrat, Credence

Panel Chair
A. Khoche, Verigy

Finance Chair
R. Chandramouli, ARM

Publicity Chair
A. Gold, Advantest

Webmaster
C. Gray, GeorgiaTech

Program Committee
R. Barth, Intel
P. Burlison, Inovys
C. J. Clark, Intellitech
W. Fister, Micron
G. Fleeman, Advantest
B. Gage, Teradyne
M. Hafed, DFT Microsystems
B. Price, NXP
R. Kapur, Synopsys
D. Keezer, GeorgiaTech
R. Lesnikoski, Sun Microsystems
M. Loranger, Formfactor
P. Muhmenthaler, Infineon
M. Roos, Roos Instruments
J. Rivoir, Verigy
N. Touba, University of Texas
C.W. Wu, Tsing Hua University

For more information, visit us on the web at: http://www.ATEVision.com

ATE Vision 2020 is sponsored by the IEEE Computer Society Test Technology Technical Council (TTTC)*.